Modem electronic products including, for example, consumer electronics, computers, telecommunication equipment and automobile electronics, use latch circuits to store data during data processing operations. Latch circuits are bistable devices having output signals assuming one of two stable states based on a signal level or signal transition of an input signal. Conventional latch circuits include dynamic and static latch circuits. Typical dynamic latches generally require less circuitry than static latches and have faster times to latch input signals representing data values. However, the electrical charge stored in a dynamic latch used for producing the one of two output signal levels tends to dissipate through current leakage and disadvantageously requires such charge to be intermittently refreshed for maintaining the proper output signal level.
In contrast, an operational state maintained by a static latch does not change over a period of time. Conventional latches generally employ a feedback between a latch output to an input of the latch to compensate for leakage preventing the state of the latch from changing. A schematic diagram of a typical prior art static latch 1 having a clocked feedback path is shown in FIG. 1. In FIG. 1, an input signal IN having a first or second logic level is provided to a first inverter 5 connected to a first switch 10 controlled by clock signal CLK. The switch 10 is further connected to a node A that is further connected to a second inverter 15. The output of inverter 15 is connected to yet a third inverter 20 and provides output signal OUT of the latch 1. The output of inverter 20 is connected to a second switch 25 that is further connected to the node A. The second switch 25 is controlled by a complement clock signal CLK. The clock signal CLK provides a signal having a complementary signal level to that of the clock signal CLK.
In operation, the signal level of the clock signal CLK determines whether the latch 1 is in a sample period or a hold period. When the clock signal CLK is at a high signal level, and correspondingly the complementary clock signal CLK is at a low signal level, the switch 10 is closed connecting the inverter 5 to node A and the switch 25 is opened disconnecting the output of inverter 20 from node A. As a consequence, the latch is in the sample period, wherein the logic level of the signal IN is inverted by the inverter 5 to generates a signal at the node A having a complementary signal level. This signal at the node A is then inverted again by the inverter 15 to produce the output signal OUT having the same signal level of the input signal IN. Accordingly, while in a sample period, the output signal OUT of the latch 1 tracks or is held to the signal level of the input signal IN. If the logic level of the input signal changes during the sample period, then the output signal OUT changes accordingly after an operational delay of the inverters 5 and 15. Also, the output signal OUT is provided to the inverter 20 which generates a signal at the open switch 25 having a complementary signal level to the output signal OUT. This inverted signal is used during the hold period.
When the clock signal CLK goes to a low signal level, the switch 10 is opened disconnecting the inverter 5 from node A and the switch 25 is closed connecting the inverter 20 to node A. As a result, the latch is in the hold period, wherein the signal generated by the inverter 20 having a complementary logic level to the input and output signals IN and OUT during the sample period is provided to the node A and inverter 15. The inverter 15 then continuously generates the output signal OUT at the same level as during the end of the sample period of the latch. Thus, the latch 1 maintains or latches the signal level of the input signal IN as the output signal OUT level near the end of the sample period. During the hold period, changes in signal level of the input signal IN have no effect on the output signal OUT.
However, each of the inverters 5, 15 and 20 produces a processing delay that is dependent on the voltage, temperature and process used to fabricate the inverters. Such delays sometimes disadvantageously operate with transitions of the clock signal CLK to provide an erroneous output signal OUT signal level. For instance, if the input signal IN undergoes a signal level transition immediately before the clock signal CLK undergoes a signal level transition, it is uncertain whether the latch will properly update the output signal OUT due to the inverter delays.
These inverter delays and switching delays in relation to the clock signal transitions, referred to as setup and hold delays, limit the speed at which the latch 1 is able to setup and hold data represented in the input signal. Conventional static latches have setup and hold delays of typically greater than 500 psec. In other words, there is a 500 psec. or greater interval before a clock signal transitions from a sample period to a hold period, wherein no change in the output signal OUT would likely occur despite a change in the input signal IN. As a result, conventional static latches are undesirably limited to processing signals having data rates of less than 1 Gigabit/sec (Gbs/sec).
Nevertheless, a need exists in the electronic industry to process data at even greater data rates. Thus, there is a corresponding need for a latch circuit configuration having reduced setup and hold delays to process data at such greater data rates.